1. Field of the Invention
The present invention relates to a semiconductor memory which has at least one V-MOS transistor, including a trench, and having a storage capacitor, and more particularly to such a semiconductor memory in which a semiconductor substrate is doped with doping concentration centers of a first conductivity type and has a buried layer which is doped with concentration centers of a second, opposite conductivity type, and in which at least two additional layers are provided and are divided by the trench and are of alternately differing conductivity types.
2. Description of the Prior Art
Semiconductor storage cells comprising a transistor (single-transistor storage cells) can be constructed from MOS transistor, which is also referred to as a selector transistor. The selector transistor is connected to a storage capacitor in which the item of information to be stored is contained as a charge. The storage cell composed of the selector transistor and the storage capacitor is connected between a word line and a bit line. Here, the word line is connected to a control input (a gate) of the selector transistor, whereas one control electrode of the transistor is connected to the bit line and the controlled electrode is connected to the storage capacitor. Single-transistor storage cells of this kind have the advantage that they can be constructed on a semiconductor substrate with a very low space requirement.
As is known in the art, MOS transistors can be produced by means of so-called V-MOS technique in which, for the control of the MOS transistor, a V-shaped trench is etched into an epitaxial layer carried on a semiconductor substrate. An insulating layer is arranged in the trench and carries a terminal for the control electrode of the MOS transistor. The channel of the MOS transistor extends in the flanks of the V-shaped trench. The two control electrodes of the MOS transistor can, for example, be arranged beside the V-shaped trench.
A semiconductor storage cell which comprises a MOS selector transistor controlled by a drive line and a storage capacitor connected to the selector transistor, and wherein the selector transistor is produced in the V-MOS technique, can now be constructed in such a manner that in a semiconductor substrate highly doped with concentration centers of one conductivity type, there is arranged a buried layer which is highly doped with concentration centers of the opposite conductivity type, that an epitaxial layer, weakly doped with concentration centers of the one conductivity type, is arranged above the buried layer and the semiconductor substrate, and that a V-MOS transistor is arranged as a selector transistor in the epitaxial layer above the buried layer, where the trench required for the formation of the selector transistor extends through the epitaxial layer into the buried layer.
This single-transistor storage cell has a very high bit density and can be produced by conventional light-exposure with structure resolutions 5 .mu.m. However, an epitaxial layer is required which impedes mass production.